1. Field of the Invention
The present invention relates to substrate bias generating devices and operating methods thereof, and more particularly to a substrate bias generating device with a configuration in which substrate bias is generated by driving two charge pumps using outputs of two logic gates using outputs of a ring oscillator as their inputs and an operating method thereof.
2. Description of the Background Art
Semiconductor devices such as a DRAM (Dynamic Random Access Memory) and so forth are semiconductor integrated circuit devices having a large number of MOS transistors formed on a single semiconductor substrate as components. Usually, in such a semiconductor integrated circuit device, the potential of a semiconductor substrate is preferably held at predetermined potential all the time.
FIG. 7 is a diagram illustrating one example of a cross-sectional structure of a part of such a semiconductor integrated circuit device. In FIG. 7, one MOS transistor and an impurity region forming an interconnection region are typically shown. Referring to FIG. 7, the MOS transistor is formed in a region in a surface of a p type semiconductor substrate 130, which includes n type impurity regions 131 and 132 as source and drain regions, and a gate electrode 133. A gate insulating film 134 is formed between gate electrode 133 and p type substrate 130. Corresponding to the voltage applied to the gate electrode 133, a channel is formed between source region 131 and drain region 132. n type impurity region 135 as an interconnection region is provided in a p type substrate 130 surface spaced from impurity region 131. Above the surface of p type substrate 130, a signal line 136 is provided between impurity regions 131 and 135 with a filter insulating film 137 with a large film thickness interposed therebetween.
In FIG. 7, when the MOS transistor is in an ON state, hot electrons and holes paired with them are produced in the vicinity of drain 132. Most of the produced hot electrons flow to drain 132. On the other hand, most of the produced holes flow to p type substrate 130. The potential of p type substrate 130 thus increases. When the potential of p type substrate 130 increases, the following problems occur.
That is, the pn junction formed by each of source region 131 and drain region 132 and p type substrate 130 and the pn junction formed by interconnection region 135 and p type substrate 130 are brought into forward bias states, respectively. As a result, leak current flows between each of source region 131, drain region 132 and interconnection region 135, and p type substrate 130, so that a channel may not be formed between source region 131 and drain region 132 in response to the voltage change for gate electrode 133, or a signal may not be transmitted through interconnection region 135 rapidly.
Also, when interconnection 136 transmits a signal at an operation power supply voltage level, if the potential of p type substrate 130 is high, a channel is likely to be formed in the surface of p type substrate 130 between impurity regions 131 and 135 due to the potential of interconnection 136. That is, a parasitic MOS transistor formed of interconnection 136, insulating film 137, n-type regions 131 and 135 is likely to operate. If such a parasitic element which is originally not a circuit element provided on semiconductor substrate 130 operates, original operation of circuit elements will suffer from bad effects.
Furthermore, a threshold value voltage Vth of a MOS transistor depends on potential of semiconductor substrate 130 in which the MOS transistor is formed. FIG. 8 is a graph illustrating relationship between threshold value voltage Vth of an n-channel MOS transistor formed on a p type semiconductor substrate and potential V.sub.BB of the p type semiconductor substrate. On the abscissa in FIG. 8, absolute values of potential V.sub.BB become larger as they are separated away from an origin. As seen from FIG. 8, threshold value voltage Vth of a MOS transistor greatly changes depending on change in voltage V.sub.BB of a semiconductor substrate in which the MOS transistor is formed in a region with high potential V.sub.BB of the semiconductor substrate (a region of -V1 or higher in the figure). However, in a region with relatively low potential V.sub.BB of the semiconductor substrate (in the figure, region of -V1 to -V2), the threshold value voltage Vth of the MOS transistor is kept substantially constant with no connection with change in potential V.sub.BB of the semiconductor substrate. Accordingly, in FIG. 7, if the potential of p type substrate 130 is about that in a negative potential region (-V1 to -V2 ) in FIG. 8, the threshold value voltages of the MOS transistor formed of gate electrode 133, insulating film 134, n-type regions 131 and 132 are not affected by fine fluctuation of potential of p type substrate 130, and it stably operates without causing punchthrough and so forth. However, if the potential of p type substrate 130 is high, since the threshold value voltage of the MOS transistor greatly changes in response to small fluctuation of potential of p type substrate 130, the MOS transistor does not operate stably.
In order to avoid such a problem as described above due to an increase in potential of p type substrate 130, negative predetermined potential about that in the potential region (-V1 to -V2) in FIG. 8 is applied to p type substrate 130, for example. Conventionally, a circuit for generating such negative predetermined potential (hereinafter referred to as substrate bias) to be supplied to a semiconductor substrate (hereinafter referred to as a substrate bias generating circuit) was provided outside a semiconductor substrate. However, a substrate bias generating circuit is recently formed on a semiconductor substrate.
FIG. 6 is a diagram illustrating entire structure of a semiconductor integrated circuit device having a substrate bias generating circuit. Referring to FIG. 6, a semiconductor integrated circuit device 100 having a MOS transistor as a component includes a functional circuit 110 and a substrate bias generating circuit 120 formed on a semiconductor substrate 130. Functional circuit 110 implements original functions of the semiconductor integrated circuit device. On the other hand, substrate bias generating circuit 120 generates negative predetermined potential as substrate bias. The generated substrate bias V.sub.BB is applied to semiconductor substrate 130. Thus, the problem of occurrence of malfunctions due to potential of semiconductor substrate 130 in functional circuit 110 can be avoided.
FIG. 4 is a diagram illustrating one example of a circuit used as the substrate bias generating circuit 120 in FIG. 6. FIG. 5 is a timing chart diagram for describing operation of the substrate bias generating circuit shown in FIG. 4. Referring to FIGS. 4 and 5, structure and operation of a conventional substrate bias generating circuit will be described below.
Referring to FIG. 4, the conventional substrate bias generating circuit includes a ring oscillator 30, a waveform shaping circuit 40, charge pump circuits 50 and 51, 2-input NOR gate 17 and a 2-input NAND gate 16.
Ring oscillator 30 includes seven inverters 1-7 connected in series. Output potential of inverter 7 at the seventh stage is inputted into inverter 1. Accordingly, an output logic level of each of inverters 1-7 switches, that is, oscillates, in a cycle corresponding to a delay time of six inverters. Respective output potentials of inverters 1, 3, 5 and 7 are substantially in phase and also output potentials of inverters 2, 4, and 6 are also substantially in phase. Output potential of inverter 3 shows phase which is delayed by a delay time by two inverters as compared to output potential of inverter 1, output potential of inverter 5 shows phase delayed by a delay time by two inverters in addition as compared to output potential of inverter 3, and output potential of inverter 7 shows phase further delayed by a delay time by two inverters as compared to output potential of inverter 5. Output potential of inverters 2, 4 and 6 and output potential of inverters 1, 3, 5 and 7 are opposite in phase. The output potential of inverter 2 shows phase different from the output potential of inverter 1 by 180.degree., the output potential of inverter 4 shows phase delayed by a delay time due to two inverters as compared to the output potential of inverter 2, and the output potential of inverter 6 shows phase delayed by a delay time due to two inverters in addition as compared to the output potential of inverter 4.
Waveform shaping circuit 40 includes p channel MOS transistors 8 and 9 and n channel MOS transistors 10 and 11 provided between a power supply Vcc and ground. Gates of transistors 8 and 11 are connected to an output terminal (node B) of inverter 5, and gates of transistors 9 and 10 are connected to an output terminal (node C) of inverter 7. Accordingly, transistor 8 and transistor 11 turn on and off complementarily to each other, and transistor 9 and transistor 10 turn on and off complementarily to each other. The potential of node B and the potential of node C show phases different by delay time by two inverters (refer to FIG. 5 (a)), so that times are short in which both of transistors 8 and 9 are in ON states, and in which transistors 10 and 11 are both in ON states. On the other hand, the potential at a connecting point E of transistors 9 and 10 rises by high voltage of power supply Vcc in response to turn-ON of both of transistors 8 and 9 and falls by ground potential in response to turn-ON of both of transistors 10 and 11. Accordingly, the potential at the node E has the same phase as that of the potential at node C, as shown by a solid line in FIG. 5 (b), and also more sharply changes than the potential at node C. That is, the potential waveform at node C is shaped and appear at node E.
The potential at node E is transmitted to node J through inverters 25 and 26. The rise and fall of potential at node E is so sharp that the potential waveform at node E is transmitted to node J with its phase being not delayed almost at all by inverters 25 and 26 (refer to the broken line in FIG. 5 (b)).
Potentials at nodes E and J are both applied to a NOR gate 17 and a NAND gate 16. Accordingly, an output of NOR gate 17 attains a high level only in a period in which both potentials of nodes E and G are at a low level as shown in FIG. 5 (d). On the other hand, an output of NAND gate 16 attains a low level in a period in which both of potentials of nodes E and G are at a high level as shown in FIG. 5 (c).
An output of NOR gate 17 is inverted by inverter 18. Accordingly, an output of inverter 18 shows phase different from an output of NAND gate 16 by substantially 180.degree. as shown in FIG. 5 (e). An output of inverter 18 and an output of NAND gate 16 are respectively inputted into charge pump circuits 50 and 51. Charge pump circuit 50 includes a capacitor 20 and a p channel MOS transistor 23 connected in series between an output terminal (node G) of inverter 18 and substrate 130, and p channel MOS transistor 24 provided between a connecting point of capacitor 20 and transistor 23 and ground. Charge pump circuit 51 includes a capacitor 19 and p channel MOS transistor 21 connected in series between an output terminal (node F) of NAND gate 16 and substrate 130, and p channel MOS transistor 22 provided between connection point of capacitor 19 and transistor 21 and ground. Each of transistors 23 and 21 is diode-connected. ON/OFF of transistor 22 is controlled by the potential at node I and ON/OFF of transistor 24 is controlled by the potential at node H. The back gate bias voltage of transistors 21 and 22 is output voltage of NAND gate 16 and back gate bias voltage of transistors 23 and 24 is output voltage of inverter 18.
In the description below, potential higher and potential lower than potential intermediate between power supply voltage Vcc and ground voltage 0V (Vcc/2) are respectively referred to as a high level voltage and a low level voltage.
In charge pump circuit 50, when the potential at node G falls to ground potential from power supply potential Vcc, the potential at node I also starts decreasing by coupling of capacitor 20 in response to that. On the other hand, in charge pump circuit 51, the potential at node F increases from ground potential to power supply potential Vcc, so that the potential at node H starts increasing by coupling of capacitor 19. When transistor 29 is brought into an OFF state with a potential increase at node H, accumulating of negative charge discharge from capacitor 20 is started at node I since a discharge path of capacitor 20 is disconnected. Thus, the potential at node I starts dropping to ground potential or below, and finally attains a negative potential (-Vcc) having an absolute value same as power supply potential Vcc. Accordingly, transistor 23 comes in an ON state and applies to substrate 130 potential (-Vcc+Vthp) higher than the potential (-Vcc) at node I by threshold value voltage Vthp of the p channel MOS transistor as substrate bias V.sub.BB. On the other hand, since transistor 22 turns on in response to fall of potential at node I, the potential at node H attains ground potential higher than the potential at node K (-Vcc+Vthp). Accordingly, transistor 21 attains an OFF state. Transistor 23 is turned on to supply negative potential (-Vcc+Vthp) to substrate 130, and a state in which transistor 21 is in an OFF state is maintained for a period in which the potential at node G is at a low level (in a period in which the potential at node F is at a high level).
On the contrary, at a fall of potential at node F, charge pump circuit 51 performs the same operation as that of charge pump circuit 50 at a fall of potential at node G.
When the potential at node F falls from power supply potential Vcc to ground potential, the potential at node H also starts decreasing by coupling of capacitor 19 in response to that. On the other hand, since the potential at node I increases in response to rise of potential at node G in charge pump circuit 50, transistor 22 is brought into an OFF state. Thus, the discharge path of capacitor 19 is cut off, so that the potential at node H decreases to negative potential (-Vcc) having the same absolute value as power supply potential Vcc. As a result, the potential at node K finally attains potential higher than the potential at node H by said threshold value voltage Vthp (-Vcc+Vthp). In charge pump circuit 50, transistor 24 turns on upon fall of potential at node H in charge pump circuit 51 to bring node I into ground potential. Accordingly, transistor 23 comes in an OFF state in charge pump circuit 50. Such a condition under which transistor 23 is in an OFF state and transistor 21 outputs negative potential (-Vcc+Vthp) to substrate 130 is maintained for a period in which the potential at node F is at a low level (a period in which the potential at node G is at a high level).
As a result of such circuit operation, negative constant potential (-Vcc+Vthp) is generated from the substrate bias generating circuit all the time.
Now, in view of reducing consumption power, a level inversion cycle of output potential of a ring oscillator, (i.e., oscillation cycle of a ring oscillator) is set to be relatively long in a conventional substrate bias generating circuit. For example, in FIG. 4, if the oscillation cycle of ring oscillator 30 is short, output potential of each of inverters 1-7 attains a high level in a short cycle. Accordingly, the consumption power at ring oscillator 30 increases. The oscillation cycle of a ring oscillator is therefor set to be relatively long. Specifically, the oscillation frequency of a ring oscillator has been approximately 200 ns in conventional cases, but it is approximately 2 .mu.s for reducing consumption current presently. When the oscillation frequency of a ring oscillator is approximately 200 ns, the consumption power of the ring oscillator is approximately 40 .mu.A, and the consumption current in the entirety of a substrate bias generating circuit is approximately 500 .mu.A, but, when the oscillation frequency of a ring oscillator is approximately 2 .mu.s, the consumption current of the ring oscillator is approximately 4 .mu.A, and the consumption current in the entirety of the substrate bias generating circuit is approximately 15 .mu.A.
For making the oscillation cycle of a ring oscillator long, a signal delay time of each inverter constituting the ring oscillator is set to be long. Accordingly, a size of a MOS transistor constituting each inverter is made small to reduce a driving capability of each inverter. When a size of a transistor constituting each inverter is small, potential at an output terminal of each inverter is not easily changed following change of output potential of an inverter at a previous stage, resulting in an increase in a delay time in each inverter. Such a measure is taken in order to make an oscillation cycle of a ring oscillator long, so that a rising time and a falling time of output potential of a ring oscillator increase. That is, rounding occurs in an output potential waveform of a ring oscillator. Accordingly, the output potential of ring oscillator 30 in FIG. 4 (the potential at nodes B and C) rises and falls slowly as shown in FIG. 5 (a). A waveform shaping circuit 40 is provided for removing such rounding of an output potential waveform of a ring oscillator.
As described above, in a conventional substrate bias generating circuit having a structure in which two charge pumps are driven using outputs of two logic gates receiving outputs of a ring oscillator, a phase of potential input into one charge pump circuit and a phase of potential input into the other charge pump circuit are set differing by 180.degree.. This is for avoiding occurrence of a period in which both of input potential to the one and input potential to the other attain a low level. If both of input potentials attain a low level, problems as follows are caused.
For example, in FIG. 4, suppose that the potential at node G falls from power supply potential Vcc to ground potential, and the potential at node F still remains at a low level. In such a case, when the potential at node I is on the decrease, the potential at node H is still low level, and a period in which transistor 24 stays in an ON state is caused. In this period, since node I is rounded, the discharge path of capacitor 20 is not broken. Accordingly, the potential at node I does not decreases to potential (-Vcc) to which it originally should decrease, and gets near ground potential 0V. On the other hand, if the potential at node G still stays at a low level at a time of potential fall at node F, since a period occurs in which transistor 22 stays in an ON state in charge pump circuit 51, the potential at node H does not sufficiently decreases and gets nearer to ground potential. As a result, substrate bias V.sub.BB gets higher than ideal potential (-Vcc+Vthp).
In order to solve such a problem, a conventional substrate bias generating circuit is made so that the potential at node F and the potential at node G are always at complementary levels. However, with high scale integration of semiconductor integrated circuit devices in these days, there are some cases where even circuit elements originally to be formed having the same sizes must be formed having different sizes because of some reasons related to occupied areas on a semiconductor substrate and the like. In the substrate bias generating circuit in FIG. 4 for example, capacitor 19 and capacitor 20 may be formed with different sizes on semiconductor substrate 130. Capacitors 19 and 20 are provided for accumulating negative charge for obtaining negative potential having a relatively large absolute value. Accordingly, capacitances of capacitors 19 and 20 must be certain values or larger. However, a size of either one of capacitor 19 and 20 may be sometimes made smaller in view of layout on a semiconductor substrate.
Accordingly, in such a case, a method is taken in which a size of the other capacitor is made large. As a result, the capacitance of capacitor 19 and the capacitance of capacitor 20 are not equal. Occurrence of unbalance between capacitances of capacitors 19 and 20 causes a period in which both of the potential at node F and the potential at node G are at a low level.
If the capacitance of capacitor 19 and the capacitance of capacitor 20 are equal to each other, the capability of capacitor 20 to keep the potential at node G constant is equal to the capability of capacitor 19 to keep the potential at node F constant. Accordingly, the time required by the potential of node G to rise in response to rise of an output of inverter 18 and the time required by the potential of node F to rise in response to the rise of an output of NAND gate 16 are equal, and a time required by the potential at node G to fall in response to the rise of an output of inverter 18 and a time required by the potential at node F to fall in response to a fall of NAND gate 16 are also equal to each other. Accordingly, as shown in FIG. 5 (f), the potential at node G is always at a high level when the potential at node F falls and the potential at node F is always at a high level when the potential at node G falls.
For example, however, if the capacitance of capacitor 20 is extremely larger than the capacitance of capacitor 19, a time required by the potential of node G to fall in response to a fall of an output of inverter 18 is considerably longer than a time required by the potential at node F to fall in response to a fall of potential at NAND gate 16. As a result, potentials at nodes F and G show waveforms as shown by a solid line and a broken line in FIG. 5 (g), respectively. As seen from FIG. 5 (g), a phenomenon occurs in which even when node F falls to a low level, the potential at node G still remains at a low level. On the other hand, if the capacitance of capacitor 19 is extremely larger than the capacitance of capacitor 20, a phenomenon occurs in which even if the potential at node G falls to a low level, the potential at node F still remains at a low level.
If the capacitance of capacitor 20 is large, as shown in FIG. 9 (a), when the potential at node F attains a low level, the potential at node G is on the gradual increase from the potential it used to be (-Vcc). Accordingly, an instance exists at which the potential at node I attains potential (-Vcc+Vthp) at which transistor 22 can be brought into an ON state in a period in which the potential at node H is on the decrease. Next, the potential change of nodes in charge pumps 50 and 51 are specifically described referring to FIG. 9 in an example in which the capacitance of capacitor 20 is extremely larger than the capacitance of capacitor 19.
FIG. 9 is a timing chart diagram illustrating operation of charge pumps 50 and 51 when the capacitance of capacitor 20 is much larger than the capacitance of capacitor 19.
The potential of node G (FIG. 9 (a)) completely attains a low level when a certain time has passed after the potential at node F rises to a high level and gradually starts rising at the time at which the potential at node F has almost completely fallen. Accordingly, as shown in FIGS. 9 (b) and (c), transistor 23 switches from an OFF state to an ON state when a certain time has passed after transistor 21 switches from an ON state to an OFF state, and, as shown in FIGS. 5 (e) and (f), transistor 22 switches from an ON state to an OFF state when a certain time has passed after transistor 24 had switched from an OFF state to an ON state. Since transistor 23 is not brought into an ON state unless the potential at node I becomes lower than the substrate potential, it switches from an ON state to an OFF state somewhat later than transistor 22. Similarly, since transistor 21 does not attain an ON state unless the potential at node H becomes lower than the substrate potential, it switches to an ON state somewhat logging behind transistor 24.
On the other hand, the potential at node H starts rising by the potential at a high level at node F in response to switch of transistor 21 into an OFF state and attains power supply potential Vcc by change of transistor 22 into an ON state thereafter, as shown by a solid line in FIG. 9 (d). Subsequently, the potential at node H starts falling in response to a fall of the potential at node F and attains -Vcc by the change of transistor 22 into an OFF state.
The potential at node I slowly rises following the potential change at node G in response to the switch of transistor 23 into an OFF state as shown by a broken line in FIG. 9 (d) to attain power supply potential Vcc. Subsequently, the potential at node I gradually falls following the fall of potential at node G in response to switch of transistor 24 into an OFF state to attain -Vcc.
Accordingly, in the period in which the potential at node I is decreasing, an instance at which both of transistors 23 and 24 attain an ON state does not occur, but when the potential at node H is decreasing, an instance .tau. occurs at which both transistors 21 and 22 are at an ON state. Accordingly, node K is instantly grounded through transistors 23 and 24 to increase the potential at node K. Such a phenomenon is caused every time the potential at node F falls, so that the potential at node K becomes stable at potential somewhat higher than (-Vcc+Vthp) as shown in FIG. 9 (g) after starting operation of ring oscillator 30.
On the other hand, if the capacitance of capacitor 19 is large, the potential at node H is gradually increasing from the potential (-Vcc) it used to be when the potential at node G attains a low level. Accordingly, an instance occurs at which transistor 24 is brought into an ON state in a period in which the potential at node I is decreasing. Accordingly, in such a case, a phenomena occurs in which node K is grounded every time the potential at node G falls. Therefore, also in such a case, the potential at node K becomes stable at potential higher than original potential (-Vcc+Vthp) as shown in FIG. 9 (g).
FIG. 10 is a graph schematically showing change of substrate potential, i.e. the potential at node K in FIG. 4, after a time of starting operation of a conventional substrate bias generating circuit.
Referring to FIG. 10, when the substrate potential is 0V immediately before the substrate bias generating circuit operates, the potential at node K actually decreases gradually as shown by the solid line. If an instance does not occur at which the potential at node G and the potential at node F simultaneously attain a low level in FIG. 4, the potential at node K, thereafter, as shown by the broken line, is stabilized at potential higher than negative potential (-Vcc) having an absolute value the same as the power supply potential by threshold value voltage Vthp of a P channel MOS transistor. If an instance occurs at which the potential at node G and the potential at node F both attain a low level simultaneously, however, the potential at node K becomes stabilized at potential higher than such potential (-Vcc+Vthp) after that.
As described above, if there exists significant difference in capacitance between capacitors 20 and 19 respectively included in charge pump circuits 50 and 51, sufficient amount of negative charge is not accumulated in these charge pump circuits. Accordingly, a conventional substrate bias generating circuit had a problem that a generating efficiency of substrate bias V.sub.BB becomes inferior if the difference in capacitance is large between a capacitor included in one of two charge pump circuits and a capacitor included in the other.
Because as the oscillation frequency of a ring oscillator is lower, the rounding of an output potential waveform of the ring oscillator is larger, the rounding is likely to be caused in the potential waveform appearing at an input end (nodes F and G in FIG. 4) of a charge pump in a substrate bias generating circuit when the capacitances of capacitors 19 and 20 in the charge pump are larger. Accordingly, since oscillation frequency of a ring oscillator is presently set low, problems as mentioned above are more serious.
In order to avoid such a problem, for example in FIG. 4, the following method is a possibility in which it is made easier that the potential at node G changes following the change in potential of an output of inverter 18 by making driving capability of inverter 18 large (when the capacitance of capacitor 20 is large), or it is made easy that the potential at node F changes following change in potential of an output of NAND gate 16 by making driving capability of NAND gate 16 large (when capacitance of capacitor 19 is large). However, according to such a method, inverter 18 and NAND gate 16 must be made large in size, resulting in a new problem of an increase in consumption power.